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Published On:
17 Jan 2012 9:46 am
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Location: Bangalore(Karnataka), India
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prabathHyderabad(Andhra Pradesh), India
Mobile: 8985129129

DIPLOMA IN VLSI ,VHDL,VERILOG,FPGA in BANGALORE in Bangalore

Education & Learning [ Professional Courses ]

Contact: +91 8985129130 (ALL OVER WORLD)
8985129129

http://www.ascentit.in/index.php?view=courses&cosid=14

MODULE 1

Introduction to VLSI

  ASIC and FPGA Design flow

  ASIC Vs FPGA

  RTL Design Methodologies                    

  Introduction to ASIC
  Verification methodologies

MODULE 2

Advanced digital Design

  Basics of digital Electronics      

  Arithmetic circuits

  Data processing circuits

  Universal logic elements

  Combination logic circuit design and Analysis

  Latches And Flip flop

  Shift Registers and counters       

  Sequential logic circuits design and Analysis

  Introduction to Finite State Machine

MODULE 3                                                   

Verilog HDL – RTL Coding and Synthesis                                                               

  Hardware Modeling Overview

  Verilog language concepts   

  Application of Verilog HDL                                        

  Verilog languages basics and constructs        

  Abstraction levels        

Introduction to Linux

  Components of UNIX system

  Directory Structure      

  Utilities and commands

  Vi Editor                                                                               

Data Types                                                                           

  Type concept                                                                      

  Nets and registers                                                    

  Non hardware equivalent variables                                

  Arrays                       

  Modules and Ports, Demo for usage of ISE for HDL usage                                                                                                                                                                                                                                                          

Verilog Operators                                                                 

  Logical operations

  Bitwise operators

  Reduction operators                                     

  Concatenation and conditional                          

  Relational and arithmetic                                     

  Shift and Equality operators                                                                                                              

Assignments                                                              

  Types of assignments                                      

  Continuous assignments

  Procedure assignments

  Blocking and Non-Blocking assignments

  Tasks and Functioning                            

Finite state Machine      

  Basic FSM Structure

  Moore Vs Mealy  

  FSM coding

Advanced Verilog HDL  

  System Tasks

  Internal variable

  Compiler directives

  File input and output

Code Coverage   

  Statement Coverage

  Branch Coverage

  Expression Coverage                                                                                 

  Toggle Coverage

  FSM State and Sequence coverage

 

Synthesis Coding Style         

  Simulation vs. Synthesis      

  Registers in Verilog 

  Unwanted latches                    

  Operator synthesis                 

  RTL Coding Style                                       

MODULE 4

Verilog Mini Project RTL CODING and Synthesis

  Project Spec Analysis

  Architecture the design

  Module level implementation

  Verification and Code coverage

  Building the top level module

  Implementing the design onto the FAGA board

MODULE 5

FPGA Architecture

  Introduction to Programmable logic

  Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB)

  Basic FPGA Architecture - Spartan 6

  Basics of Configuration (Configuration Process, Modes, Configuration Pins &   Startup Sequence)

  Daisy chaining

 

FPGA Design Flow:

  Xilinx tool Flow

  Reading Reports

  Implementing IP cores

  Pin Planning using Plan Ahead

  Static timing Analysis

  Global timing Constraints

Optimal FPGA Design:

  Synchronous Design Techniques

  HDL Coding Techniques

  FPGA Design Techniques

  Synthesis Techniques & Implementation Options

  Achieving Timing Closure

  Path Specific Constraints

  Advanced IO Timing

  Area Planning using Plan Ahead & Smart Guide Technology    

MODULE 6

STATIC TIMING ANALYSIS

  Introduction to STA

  Comparison with DTA

  Timing path and constraints

  Different types of clocks

  Clock domain and variations

  Clock distribution networks

  How to fix timing failure   

MODULE 7

CMOS FUNDMENTALS

  Non ideal characteristics

  BJT VS FET

  CMOS Characteristics

  CMOS circuit design

  Transistor sizing

  Layout and stick diagrams

  CMOS Processing steps

  Fabrications

  CMOS Technology – Current

MODULE 8

VHDL – RTL Coding and synthesis

   VHDL introduction and applications

   Comparison between VHDL and Verilog

   Design units

   Data types

   Operators

   Concurrent statements

   Sequential statements

   File I/O Operations

   Test bench

   Synthesis issues

   FSM coding styles

MODULE 9

VHDL Mini project – RHL Coding and synthesis

  Project Spec Analysis

  Architecture the design

  Module level implementation

  Verification and Code coverage

  Building the top level module

  Implementing the design onto the FAGA board

 

MODULE 10

Verification methodologies

  Directed VS Random

  Introduction to Functional Verification

  Verification Tools, Stimulus and Response

  Introduction to BFMs

  Monitors and reference models

  Introduction to Verification Plan

  Coverage driven verification

  Different types of Code Coverage

  Verification planning and managements

MODULE 11

System verilog HVL

  Introduction to system verilog

  New data types

  Tasks and functions

  Interfaces

  Clocking blocks

OOP AND RANDOMIZATION

  OOP Basics

  Classics – objects and handles

  Polymorphism and inheritance

  Randomization

  Constraints

 

THREADS AND VIRTUAL INTERFACES

  Fork join

  Fork join_any

  Fork joins none

  Event controls

  Mailboxes and semaphores

  Virtual interfaces

  Transactions

  Building verification environment

  Test cases

Callbacks

  Fascade class

  Building reusable transistors

  Inserting callbacks

  Registering callbacks

FUNCTIONAL COVERAGE

  Coverage models

  Cover points and bins

  Cross coverage

  Regression testing

Module 12

Verification planning and management

  Verification plan

  TB architecture

  Coverage model tracking the simulation process

  Building regression test suite

  Test suite optimization

Module 13

MINI PROJECT VERIFICATION AND RTL SIGN-OFF

  Project specification analysis

  Creating test bench architecture

  Defining transaction

  Implementing the transactors

  Building the top level verification environment

  Generating the functional and code coverage reports

Module 14

Assertion Based Verification – PSL

  Introduction to ABV

  PSL Flavors

  Implication Operators

  Simple properties

  PSL SERE

  Complex sequences

  Verification unit

  Reusable assertion ips

Module 15

Introduction to VMM

  VMM – Layered architecture

  VMM Message services and utilities

  VMM Environment

  Atomic and scenario generators

  VMM channel

  Callbacks

  Test cases

  VMM Tutorial

MODULE 16

Low Power Design and verification

  Low power design Techniques

  CMOS – Static and Dynamic power

  Power Format – UPF and CPF

  Power Aware Simulation

MODULE 17

Perl

  Introduction to Perl

  Functions and statements

  Numbers, strings and Quotes

  Variables

  Comments and Loops

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